NVIDIA Uses Its Own Vera CPU to Design Next-Gen Chips Faster

NVIDIA has deployed its Vera CPU inside the electronic design automation (EDA) workflows used to build its next-generation chips, creating a self-reinforcing loop where each CPU generation helps design the one after it. Early testing on production-class workloads shows up to 1.5x higher performance on Cadence Jasper formal verification and Synopsys VCS simulation tools, both running on the same core counts as the comparison baseline. NVIDIA is collaborating with both EDA vendors on profiling and software tuning to extend those gains across a broader set of workflows.

What happened

Detail	Fact
CPU deployed	NVIDIA Vera
CPU cores	88 custom NVIDIA Olympus cores
Memory subsystem	LPDDR5X
Interconnect	Second-generation NVIDIA Scalable Coherent Fabric
Performance gain (selected workloads)	Up to 1.5x on Cadence Jasper and Synopsys VCS
EDA partners	Cadence, Synopsys
Next CPU in roadmap	Rosa, powered by Rigel core

NVIDIA has put its Vera CPU to work running the EDA (electronic design automation) software that engineers use to validate and build chips. EDA covers the simulation, formal verification, and digital implementation stages that a chip design must pass through before it can be sent to a fab. These stages are CPU-bound: they rely on fast individual cores, low-latency memory, and steady throughput rather than the massively parallel compute that GPUs provide.

The two tools tested are among the most widely used in the industry. Cadence Jasper is a formal verification platform that applies mathematical proof techniques and machine learning to catch design bugs early. Synopsys VCS is a functional verification simulator used to validate chip behaviour before fabrication. Both ran on the same number of cores in NVIDIA’s comparison test and delivered up to 1.5x higher performance on selected production-class workloads.

Why does CPU performance matter for chip design?

GPU and AI acceleration have sped up parts of the EDA pipeline, but logic simulation, formal verification, and portions of digital implementation still depend on strong single-core performance and efficient memory systems. A faster CPU shortens individual verification runs and lets engineers run more regression tests (large batches of automated checks) within the same development window. That means more design alternatives explored and fewer costly errors caught late.

Vera’s architecture targets exactly these needs: 88 Olympus cores, LPDDR5X memory for high bandwidth and low latency, and a coherent fabric that keeps the memory view consistent across cores. According to NVIDIA, these traits matter most for workloads that mix latency-sensitive jobs with large-scale farm-based regression testing.

The self-referential strategy

What makes this deployment notable is the feedback loop it creates. NVIDIA is using a CPU it designed to design the CPUs and GPUs that come after it. Each generation of silicon and software tuning feeds into the next. That is not just a marketing angle: it means NVIDIA’s own engineering teams are a real-world stress test for Vera’s EDA performance, and any software optimisations negotiated with Cadence and Synopsys will show up in shipping product cycles.

The next step on the roadmap is Rosa, the successor to Vera, which will be powered by the Rigel core. NVIDIA has not published a timeline beyond naming Rosa as the next-generation platform.

Our take

A 1.5x improvement on selected workloads is a real gain in an industry where verification bottlenecks routinely add weeks to schedules. The caveat is “selected workloads”: NVIDIA is transparent that these are early results on specific tests, not a blanket improvement across all EDA tasks. The deeper collaboration with Cadence and Synopsys on profiling and tuning is probably where the more durable gains will come from.

For businesses outside the semiconductor world, the relevant takeaway is structural. NVIDIA is building vertical integration at the silicon level: its CPUs design its GPUs, which train its AI, which feeds back into EDA tools. That tightening loop makes it harder for competitors to match NVIDIA’s iteration speed, which has downstream effects on AI hardware availability and pricing for everyone who buys cloud compute.

If you are tracking how AI infrastructure investments translate into real capability changes, our AI news coverage follows this layer of the stack regularly. And if you are thinking about how to integrate AI tools into your own workflows, our AI integration services can help you map what is practical today versus what is still roadmap noise.

Source: NVIDIA Blog